Security arrangement for a telecommunications exchange system

ABSTRACT

A security arrangement for a telecommunications system having two security planes, a plurality of peripherals, a plurality of peripheral communication controllers; and switching arrangements interconnecting the peripheral communication controllers. To determine a faulty security plane, a duplex path is provided between the controllers, and, using this path, a controller automatically performs path checks on one of the security planes. If the plane is found to be not faulty, the controller sends data associated with that plane to the peripheral with which it is in communication.

BACKGROUND OF THE INVENTION

The present invention relates to a security arrangement for atelecommunications exchange system employing switching networks whichhandle time division multiplexed information.

Switching networks which handle time division multiplexed information"make" and "break" the communication paths in synchronism with theappearance of the multiplexed information. Typically a time divisionswitching network suitable for handling pulse code modulated speechsamples includes (i) a receive equipment including a receive samplestore for the incoming path of each time division multiplex junction,(ii) a transmit equipment including a transmit sample store for theoutgoing path of each time division multiplex junction and (iii) anelectronic switching network providing sample information transfer pathsbetween the various channel storage locations of the receive samplestores and the various channel storage locations of the transmit samplestores. Each sample store comprises a plurality of sample informationstorage locations. On the incoming or receive side of the exchange thesuccessive channels of the received t.d.m. transmission are sequentiallyfed into successive storage locations of the appropriate receive samplestore; whereas on the outgoing or transmit side of the exchange thechannel storage locations of each transmit sample store are successivelyfed on to the outgoing path of the associated junction.

Such exchange systems require security arrangements and find applicationin the "SYSTEM X" type of telecommunications exchanges in which lineconcentrators and digital route switching are provided, including aperipheral card controller. Exchanges of this type are provided with twosecurity planes. The main fault detection mechanism used for speechwithin the peripheral card controller is a discrepancy detector whichcompares the data, on a per time slot basis, from both security planesand indicates a fault when not equal. This is a good mechanism for faultdetection but does not indicate which security plane is faulty. As onlyeight bits will be switched through the switch, no check code can beused to determine the faulty plane. In normal operation, Plane 0 datawill always be chosen.

Accordingly an aim of the present invention is to provide a securityarrangement in which the faulty security plane is determined by the useof path check equipment which executes a path check algorithm.

SUMMARY OF THE INVENTION

According to the present invention, there is provided a securityarrangement for a telecommunications system having two security planes,a plurality of peripheral card controllers, a plurality of peripherals;and switching arrangements interconnecting the peripheral cardcontrollers, wherein, to determine a faulty security plane a path isprovided between the controllers, and, using this path, a controllerautomatically performs path checks on one of the security planes, and iffound to be not faulty, the controller sends data associated with thatplane to the peripheral with which it is in communication.

According to an aspect of the present invention the path checks areperformed by the controller transmitting path check patterns to theswitching arrangement for all timeslots for which a discrepancy isdetected.

According to a further aspect of the invention, the controller isarranged to monitor data received from the switching arrangement lookingfor the path check patterns being returned from a controller at theother end of the path which will be similarly performing a path checkingoperation.

BRIEF DESCRIPTION OF THE DRAWING

An embodiment of the present invention will now be described withreference to the following drawings wherein:

FIGS. 1 and 1a show a block diagram of a peripheral card controller,when FIG. 1a is placed to right of FIG. 1,

FIG. 2 shows a flow diagram of Timeslot Transitions,

FIG. 3 shows a flow diagram of Peripheral card Controller Transitions,

FIG. 4 shows a flow diagram of an Input Loop routine,

FIG. 5 shows a flow diagram of a Sync Input routine,

FIGS. 6, 6a and 6b show a flow diagram of a Switch Input routine, whenFIG. 6a is placed below FIG. 6, and FIG. 6b is placed to the right ofFIG. 6a,

FIGS. 7 and 7a show a flow diagram of a Peripheral Data routine, whenFIG. 7a is placed to the right of FIG. 7,

FIG. 8 shows a flow diagram of a Reset Alarm routine,

FIGS. 9 and 9a show a flow diagram of a Sync Function routine, when FIG.9a is placed to the right of FIG. 9,

FIG. 10 shows a flow diagram of an Inhibit Check Persist 1 routine,

FIG. 11 shows a flow diagram of an Inhibit Check Persist 2 routine,

FIG. 12 shows a flow diagram of a Fault Check 1 routine,

FIG. 13 shows a flow diagram of a Fault Check 2 routine,

FIG. 14 shows a flow diagram of a Low Frequency Sync routine,

FIG. 15 shows a flow diagram of a Path Check Inhibit 1 routine,

FIG. 16 shows a flow diagram of a Path Check Inhibit 2 routine,

FIG. 17 shows a flow diagram of a Checking routine,

FIG. 18 shows a flow diagram of a Persisting routine,

FIGS. 19, 19a, 19b and 19c show a flow diagram of a Looking for Pattern0 routine, when FIG. 19a is placed to the right of FIG. 19, and FIG. 19bis placed below FIG. 19, and FIG. 19c is placed below FIG. 19a,

FIG. 20 shows a flow diagram of a Looking for Pattern 1 routine,

FIG. 21 shows a flow diagram of a Path Check Continue routine,

FIGS. 22 and 22a show a flow diagram of a Plane Select routine, whenFIG. 22a is placed to the right of FIG. 22,

FIG. 23 shows a flow diagram of a Bias Transmit routine,

FIGS. 24 and 24a show a flow diagram of a Valid routine, when FIG. 24ais placed below FIG. 24,

FIG. 25 shows a flow diagram of a Path Check Checking for Discrepancyroutine,

FIGS. 26 and 26a show a flow diagram of a Path Check Pattern 1 routine,when FIG. 26a is placed to the right of FIG. 26, and,

FIG. 27 shows a flow diagram of a Path Check Bias routine.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Referring to FIGS. 1 and 1a, a functional block diagram is shown of aperipheral card controller.

Sync Detect and Validate Circuit (A)

This circuit receives data, control and sync information together withan 8MHz clock signal in respect of security Plane 0. The circuit detectsand validates the sync information and generates a sync data signal fordemultiplexer C, select sync and clock circuit D and multiplexer M.

Sync Detect and Validate Circuit (B)

This circuit receives data, control and sync information together withan 8MHz clock signal in respect of security Plane 1. The circuit detectsand validates the sync information and generates a sync data signal forselect sync and clock circuit D, demultiplexer E, and multiplexer N.

Demultiplexer (C)

This circuit demultiplexes the data, control and sync information inrespect of Plane 0, under the control of circuit A, and generates acontrol signal C0, a speech signal SA0, a speech signal SB0 and a syncsignal S0.

Select Sync and Clock Circuit (D)

This circuit receives the 8MHz clock signal from Plane 0 and Plane 1,the signals generated by circuits (A) and (B), and a program signal,PROG. The circuit generates in accordance with the received signalsvarious clock and enable signals CLK, FS for presentation to circuits(F,G,H,J,K,L), and generates signals for, and receives signals fromperipheral equipment PERIPH.

Demultiplexer (E)

This circuit demultiplexes the data control and sync information inrespect of Plane 1, under the control of circuit B, and generates acontrol signal C1, a speech signal SA1, a speech signal SB1 and a syncsignal S1.

Bit Aligners (F and G)

These circuits re-time the signals SA0, SB0, C0 and SA1, SB1, C1respectively under the control of signals CLK and FS, generated bycircuit D. Signals SA0, SB0, SA1, SB1 are then presented to the speechalarm detection and data selection circuit J, and signals C0, C1 arepresented to the control validation and processing circuit H.

Control Validation and Processing Circuit (H)

This circuit generates control signals for presentation to the bitaligners L and K, and a reset RST signal and a control signal, CTL0 forexternal equipment. The circuit receives signals C0 and C1 frombit-aligners F and G, and a sync signal from circuit D. The circuit alsoreceives an external alarm signal EXT, a request to sent signal RTS, acontrol signal CLTI and a peripheral loopback signal LBK from externalequipment.

Speech Alarm Detection and Data Selection Circuit (J)

This circuit determines the conditions which permit speech data receivedfrom bit aligners F and G to be despatched on lines SD1 and SD2. It alsodetermines the condition which permit the speech data received on linesSD3, SD4 to be despatched by way of bit aligners L and K. The circuit iscontrolled by a swop signal SWP, received from external equipment and bythe peripheral loopback signal LBK received from circuit H.

Bit Aligners (L and K)

These circuits re-time the signals received from circuit J in accordancewith signals FS and CLK from circuit D. The circuits are controlled bythe control signals from circuit H. Bit aligner L handles data inrespect of Plane 0 and generates speech signals SAA0, SBB0 and a controlsignal CO0, and bit aligner K handles data in respect of Plane 1 andgenerates speech signals SAA1, SBB1 and sync signal CO1.

Multiplexer (M)

This circuit multiplexes the speech signals SBB0, SAA0 in respect ofPlane 0, and generates a multiplexed output data control signal on lineDC0. The multiplexer is controlled by control signal CO0, sync signal S0and a sync detect signal from circuit A.

Multiplexer (N)

This circuit multiplexes the speech signals SAA1, SBB1 in respect ofPlane 1, and generates a multiplexed output data control signal on lineDC1. The multiplexer is controlled by control signal CO1, sync signalS1, and a sync detect signal from circuit B.

When a single fault occurs discrepant data may be received by aperipheral card controller in several time slots. It is assumed thatsimultaneous faults do not occur in both security planes at the sametime and that any previous faults, that have not yet been repaired, havebeen isolated by the use of locking and idle patterns. Consequently onlyone equipment failure at a time needs to be catered for by the pathchecking algorithm. Therefore if it can be determined which plane hasthe faulty equipment and which time slots are receiving corrupted datafrom the faulty equipment, then it is possible to accurately selectuncorrupted data.

To determine a faulty security plane the peripheral card controllerrelies on a duplex path through the switch to another peripheral cardcontroller. Using this path it performs path checks on security Plane 1.If the path checks succeed the peripheral card controller sends Plane 1data to the peripheral. If the path checks fail, the peripheral cardcontroller sends Plane 0 data to the peripheral. The peripheral cardcontroller reports the results of the path checks to a control system.The path checks are performed by the peripheral card controllertransmitting path check patterns to the switch for all timeslots onwhich it detects discrepancy. The peripheral card controller monitorsthe data received from the switch looking for the path check patternsbeing returned from the peripheral card controller at the other end ofthe duplex path which will have seen discrepant data and will similarlybe path checking. If the patterns are received from the switch, plane 1is considered good. If the patterns are not received within a twoMultiframe timeout, plane 1 is considered bad. Two patterns are used forperforming path check. These are:

    Bit 0 1 2 3 4 5 6 7

Pattern 0=1 0 1 1 0 1 1 0

Pattern 1=0 1 0 0 1 0 0 1

The path check patterns that are transmitted into the switch will bealternated each frame from the commencement of path checking andsynchronised by a two frame sync signal derived from the sync stream.Path checking is synchronised across all peripheral card controllers viathe Multiframe sync. The path check algorithm relies on the statedescribing the condition of the peripheral card controller as a wholeand on the state describing the condition of a speech timeslot performedfor each of the 64 timeslots received by the peripheral card controller.

The peripheral card controller will be in one of six possible states:

Checking for Discrepancy.

Persisting Discrepancy.

Looking For Pattern 0.

Looking For Pattern 1.

Path Check Continue.

Path Check Complete.

Each speech timeslot is in one of two possible states:

(a) No fault, Path Checking Off

For each timeslot in the `no fault` state the peripheral card controllerperforms a discrepancy check on the data received from the switch. If adiscrepancy is detected, the `Path Checking On` state is entered forthat timeslot.

(b) Fault, Path Checking On

If the peripheral card controller is path checking, that is, if theperipheral card controller is either in the Looking for Pattern 0,Looking for Pattern 1 or Path Check Continue state, then the peripheralcard controller will perform path checks for this timeslot. A timeslotbeing path checked will transmit path check patterns into the switch onPlane 1. If the peripheral card controller state returns to `checkingfor discrepancy`, all timeslot states will enter the no fault, PathChecking Off state. The timeslot state transistions are shown in FIG. 2.

Step 1. This step checks for a discrepancy, Path Check patterns will notbe transmitted for timeslots in this state.

Step 2. If the peripheral card controller is path checking then PathCheck patterns will be transmitted for timeslots in this state. A resetalarm will return all timeslots to Step 1.

The speech discrepancy algorithm of the peripheral card controller hasthe following six states:

Checking for Discrepancy

The peripheral card controller is performing discrepancy check on thedata being received from the switch. The peripheral card controlerenters the `persisting discrepancy` state when a discrepancy isdetected. A speech fault register is updated to contain the currenttimeslot number and fault state `Looking for Pattern 0`.

Persisting Discrepancy

The peripheral card controller is persisting the discrepancy detected.If the discrepancy persists, the peripheral card controller will, at theend of a Multiframe, enter the `Looking For Pattern 0` state and a twoMultiframe Timeout will commence. If the discrepancy does not persist,the peripheral card controller will, at the end of a Multiframe, returnto the `checking for discrepancy` state. The persistance algorithmcounts the number of discrepant frames within a Multiframe timeinterval. If `m` faulty frames are detected, where `m` is held in aregister, where 0 is less than m, which is less than 5, in a Multiframe,the discrepancy will be persisted.

Looking for Pattern 0

The peripheral card controller looks for Pattern 0 occurring in any ofthe 64 Timeslots. The first timeslot to provide Pattern 0 will be notedin the speech fault register, and the fault state updated to `LookingFor Pattern 1`. For the rest of the algorithm the peripheral cardcontroller will only concern itself with this one timeslot. When Pattern0 is found, the peripheral card controller enters the `Looking ForPattern 1` state.

Looking for Pattern 1

The peripheral card controller will remain in this state for one frame.Path check pattern 0 has been detected and the peripheral cardcontroller is now checking for path check pattern 1. If pattern 1 isreceived in the timeslot whose number is held in the speech faultregister, the peripheral card controller state will change to the `PathCheck Continue` state and the Fault state of the register will beupdated to `Path Check Continue`. If pattern 1 is not received, in thetimeslot whose number is held in the speech fault register, theperipheral card controller will return to the `Looking for path checkpattern 0` state but still concerning itself with the one timeslot, thatis, it will look for Pattern 0 occurring in the timeslot whose number isheld in the speech fault register.

Path Checking Continue

The path checks have been completed successfully for the timeslot inquestion. The peripheral card controller will continue to transmit testpatterns into the switch until the peripheral card controller statechanges to `Path Checking Complete`.

Path Checking Complete

The peripheral card controller will go to `Path Check Complete` uponcompletion of the two Multiframe timeout, which started when theperipheral card controller first went to `Looking For Pattern 0`. Aperipheral card controller in the `Path Checking Complete` state hascompleted its path check sequences. The fault state of the switch cannow be determined by reading the speech fault register. The faultytimeslot number will indicate the timeslot that was tested for PathCheck Patterns. The fault type number usually indicates which plane ofthe switch is faulty as follows:

Looking for path check pattern 0--Plane 1 faulty.

Looking for path check pattern 1--Plane 1 faulty.

Path Check Complete--Plane 0 faulty.

The algorithm now has sufficient information to ensure that good data issent to the peripheral. The peripheral card controller will normallysend a `request to send alarm` to the control system when the peripheralcard controller enters the `Path Checking Complete` state. If theperipheral card controller receives a `reset alarms` command from thecontrol system, all speech timeslot states are set to `no fault`, PathChecking Off, the peripheral card controller state is set to `checkingfor discrepancy` and the `request to send alarm` flag is reset. Theperipheral state transistions are shown in FIG. 3.

STEP 1. This step performs a discrepancy checking operation. If adiscrepancy is found step 2 is performed.

STEP 2. This step checks to see if the discrepancy is persisting. If adiscrepancy persists step 3 is performed. If after sixteen frames thediscrepancy has not persisted then a time-out TM occurs and step 1 isrepeated.

STEP 3. This step looks for pattern 0. If pattern 0 is found step 4 isperformed. If pattern 0 is not found then the occurrance of thethirty-two frame timeout TMT will cause step 6 to be performed.

STEP 4. This step looks for pattern 1. If pattern 1 is found, step 5 isperformed. If pattern 1 is not found step 3 is repeated. After thirtytwo frames, a time-out TMT occurs and step 6 is performed.

STEP 5. This step continues the path check bus biases to Plane 1. Afterthirty-two frames a time-out TMT occurs and step 6 is performed.

STEP 6. This step is performed when the path check is complete.

During Steps 2-6, a processor message PM will cause step 1 to berepeated.

FIG. 4 shows the Input Loop routine.

STEP 1. This step performs an input waiting operation.

STEP 2. This step acknowledges when an input has been received.

STEP 3. This step determines which input routine is received as follows:

Sync Input SI, in which case step 4 is performed,

Data from Switch DS, in which case step 5 is performed,

Data from a Peripheral, DP, in which case step 6 is performed, or,

Reset Alarms, RA, in which case step 7 is performed.

STEP 4. This step is a Sync Input routine and is shown in FIG. 5.

STEP 5. This step is a Switch Input routine and is shown in FIG. 6.

STEP 6. This step is a Peripheral Input routine and is shown in FIG. 7.

STEP 7. This step is a Reset Alarm routine and is shown in FIG. 8.

FIG. 5 shows the Sync Input routine, SI.

STEP 1. This step enters the Sync Input routine.

STEP 2. This step determines the lock state of the switch as follows:

No Lock NL, in which case step 3 is performed.

Lock Plane 0 LP0, in which case step 4 is performed.

Lock Plane 1 LP1, in which case step 4 is performed.

Path Check inhibited PLI in which case step 4 is performed.

STEP 3. This step performs the Sync Function as described with referenceto FIG. 9.

STEP 4. This step determines the input state of the frame sync FS andlow frequency sync LFS. When the states are 1,0 respectively step 5 isperformed, and when the states are 1,1, step 6 is performed.

STEP 5. This step performs an Inhibit Check Persist 1 routine and isdescribed with reference to FIG. 10.

STEP 6. This step performs an Inhibit Check Persist 2 routine and isdescribed with reference to FIG. 11.

STEP 7. This step exits the Sync Input routine.

FIGS. 6, 6a and 6b show a Switch Input routine, SWI.

STEP 1. This step causes the Switch Input routine to be entered.

STEP 2. This step determines the clock state. If the Plane 1 clocks, P1CLKS are faulty, step 3 is performed. If the clocks are not faulty CLKSOK, step 7 is performed. If the Plane 0 clocks are faulty, P0 CLKS step5 is performed.

STEP 3. This step sends Plane 0 data to the peripheral.

STEP 4. This step ensures that all subsequent plane selections areignored.

STEP 5. This step sends Plane 1 data to the peripheral.

STEP 6. This step ensures that all subsequent plane selections areignored.

STEP 7. This step determines the lock state, as follows:

Path check inhibit PCI. If this state exists, step 8 is performed.

Lock to Plane 0, LP0. If this state exists, step 9 is performed.

No Lock, NL. If this state exists, step 12 is performed.

Lock to Plane 1, LP1. If this state exists step 11 is performed.

STEP 8. This step performs a Path Check Inhibit 1 routine as describedwith reference to FIG. 15.

STEP 9. This step performs a Path Check Inhibit 2 routine as describedwith reference to FIG. 16.

STEP 10. This step ensures that Plane 0 data is sent to the peripheral.

STEP 11. This step performs a Path Check Inhibit 2 routine, as describedwith reference to FIG. 16.

STEP 12. This step determines the state of the peripheral cardcontroller, as follows:

Check for Discrepancy, CFD. If this state exists step 13 is performed.

Persisting Discrepancy, PD. If this state exists step 14 is performed.

Looking for Pattern 0, LP0. If this state exists step 15 is performed.

Looking for Pattern 1, LP1. If this state exists step 16 is performed.

Path Check Continue, PCC. If this state exists step 17 is performed.

Path Check Complete, PCCM. If this state exists step 18 is performed.

STEP 13. This step performs a Checking routine as described withreference to FIG. 17.

STEP 14. This step performs a Persist routine as described withreference to FIG. 18.

STEP 15. This step performs a Looking for Pattern 0 routine as describedwith reference to FIG. 19.

STEP 16. This step performs a Looking for Pattern 1 routine as describedwith reference to FIG. 20.

STEP 17. This step performs a Path Check Continue routine as describedwith reference to FIG. 21.

STEP 18. This step performs a Plane Select routine as described withreference to FIG. 22.

STEP 19. This step ensures that Plane 1 data is sent to the peripheral.

STEP 20. This step causes exit from the Switch Input routine.

FIG. 7 and 7a show a Peripheral Data routine, PDT.

STEP 1. This step causes the Peripheral Data routine to be entered.

STEP 2. This step determines the state of the peripheral card controllerand the resulting action as follows:

Checking for Discrepancy, CFD. If this state exists, step 3 isperformed.

Persisting Discrepancy, PD. If this state exists, step 4 is performed.

Looking for Pattern 0, LP0. If this state exists, step 6 is performed.

Looking for Pattern 1, LP1. If this state exists, step 6 is performed.

Path Check Continue, PCC. If this state exists, step 6 is performed.

Path Check Complete, PCCM. If this state exists, step 5 is performed.

STEP 3. This step transmits data for Plane 0 and data for Plane 1 to theswitching arrangement.

STEP 4. This step transmits data for Plane 0 and data for Plane 1 to theswitching arrangement.

STEP 5. This step transmits data for Plane 0 and data for Plane 1 to theswitching arrangement.

STEP 6. This step determines whether the path state is path checking onor off. If the off state is determined, step 7 is performed. If the onestate is determined, step 8 is performed.

STEP 7. This step transmits data for Plane 0 and data for plane 1 to theswitching arrangement.

STEP 8. This step determines if the transmit bit is set to pattern 1. Ifit is not set, step 9 is performed if it is set, step 10 is performed.

STEP 9. This step transmits data for Plane 0, and the pattern 0 to Plane1.

STEP 10. This step transmits data for Plane 0, and pattern 1 to Plane 1.

STEP 11. This step performs a Bias Transmit routine to be performed asdescribed with reference to FIG. 23.

STEP 12. This step causes exit from the peripheral data routine.

FIG. 8 shows a Reset Alarm routine RA.

STEP 1. This step causes the Reset Alarm routine RA to be entered.

STEP 2. This step sets the clocks to not faulty.

STEP 3. This step sets the peripheral card controller state to: Checkingfor a Discrepancy.

STEP 4. This step sets the path states for all timeslots to Checking fora Discrepancy.

STEP 5. This step resets a request to send an alarm.

STEP 6. This step sets the faulty timeslot number in the speech faultregister to 00 in hexadecimal.

STEP 7. This step sets the fault type to 00.

STEP 8. This step sets the fault count to zero.

STEP 9. This step resets the speech fault bit.

STEP 10. This step resets the low frequency sync counter.

STEP 11. This step sets the transmit bit to zero.

STEP 12. This step causes exit from the reset alarm routine.

FIGS. 9 and 9a show the Sync Function, SF.

STEP 1. This step causes the sync function to be entered.

STEP 2. This step determines the state of the peripheral card controllerand the resulting action as follows:

Check for Discrepancy, CFD. If this state exists, step 3 is performed.

Persisting Discrepancy, PD. If this state exists, step 4 is performed.

Looking for Pattern 0, LP0. If this state exists, step 7 is performed.

Looking for Pattern 1, LP1. If this state exists, step 7 is performed.

Path Check Continue, PCC. If this state exists, step 7 is performed.

Path Check Complete, PCCM. If this state exists, step 10 is performed.

STEP 3. This step sets the fault counter to zero.

STEP 4. This step determines the state of the frame sync, FS, and lowfrequency sync LFS. If the states are 1,0 respectively, step 5 isperformed. If the states are, 1,1, step 6 is performed.

STEP 5. This step causes the Fault Check 1 routine to be performed asdescribed with reference to FIG. 12.

STEP 6. This step causes the Fault Check 2 routine to be performed, asdescribed with reference to FIG. 13.

STEP 7. This step determines the state of the Frame Sync FS and the lowfrequency sync LFS. If the states are 1,0 respectively step 8 isperformed. If the states are 1,1, step 9 is performed.

STEP 8. This step toggles the transmit bit.

STEP 9. This step causes the Low Frequency Sync routine, to beperformed, as described with reference to FIG. 13.

STEP 10. This step causes exit from the Sync Function routine.

FIG. 10 shows an Inhibit Check Persist 1 routine. ICP1.

STEP 1. This step causes the inhibit check persist 1 routine to beentered.

STEP 2. This step checks whether the speech fault bit is set. If not,step 6 is performed, if the bit is set, step 3 is performed.

STEP 3. This step checks whether the fault count is less then the valuestored. If it is not step 5 is performed. If it is less, then step 4 isperformed.

STEP 4. This step causes a fault counter to be incremented.

STEP 5. This step causes the fault bit to be reset.

STEP 6. This step causes exit from the Inhibit Check Persist 1 routine.

FIG. 11 shows an Inhibit Check Persist 2 routine, ICP2.

STEP 1. This step causes the Inhibit Check Persist 2 routine to beentered.

STEP 2. The step causes a check on the speech fault bit to be made. Ifthe bit is set, step 3 is performed. If the bit is not set step 4 isperformed.

STEP 3. This step determines whether the fault count is greater then thevalue stored minus one. If it is, step 5 is performed, If it is not,step 8 is performed.

STEP 4. THis step determines whether the fault count is less than thevalue stored. If it is, step 8 is performed. If it is not, step 5 isperformed.

STEP 5. This step determines whether a plane is locked to either Plane 1or Plane 0. If it is, step 7 is performed. If it is not step 6 isperformed.

STEP 6. This step causes a request to send an alarm to be raised.

STEP 7. This step causes a speech discrepancy flag to be set in thefault register.

STEP 8. This step causes the fault count to be reset.

STEP 9. This step causes a fault bit to be reset.

STEP 10. This step causes exit from the Inhibit Check Persist 2 routine.

FIG. 12 shows the Fault Check 1 routine, FC1.

STEP 1. During this step the FC1 routine is entered.

STEP 2. This step checks if the speech fault bit is set. If not, step 6,exit FC1 is performed. If the bit is set, step 3 is performed.

STEP 3. This step checks if the fault count is less then the valuestored. If not, step 5 is performed. If it is less then the valuestored, step 4 is performed.

STEP 4. This step increments the fault count.

STEP 5. This step resets the speech fault bit.

STEP 6. This step causes exit from the Fault Check 1 routine.

FIG. 13 shows the Fault Check 2 routine FC2.

STEP 1. During this step the Fault Check 2 routine is entered.

STEP 2. This step checks if the fault bit is set. If not, step 9 isperformed. If it is set, step 3 is performed.

STEP 3. This step checks if the fault count is greater than the valuestored minus one. If it is not, step 10 is performed. If it is greater,step 4 is performed.

STEP 4. This step, at the start of time slot 1 sets the peripheral cardcontroller to the state: Looking for Pattern 0.

STEP 5. This step resets the low frequency sync counter.

STEP 6. This step sets the transmit bit to pattern 0.

STEP 7. This step resets the fault count.

STEP 8. This step resets the speech fault bit.

STEP 9. This step checks if the fault count is less than the valuestored. If it is not, step 4 is performed. If it is less, step 10 isperformed.

STEP 10. This step sets the peripheral card controller to the state:Checking for Discrepancy.

STEP 11. This step sets the path state to path checking off for alltimeslots, step 7 is then performed.

STEP 12. This step causes exit from the Fault Check 2 routine.

FIG. 14 shows the Low Frequency Sync routine LFS.

STEP 1. During this step the Low Frequency Sync routine is entered.

STEP 2. This step checks if the low frequency sync counter is greaterthan zero. If it is, step 3 is performed, if it is not, step 5 isperformed.

STEP 3. This step changes the state of the peripheral card controller toPath Check Complete.

STEP 4. This step sets a request to send an alarm.

STEP 5. This step increments the low frequency sync counter.

STEP 6. This step sets the transmit bit to pattern 0.

STEP 7. This step exits the Low Frequency Sync routine.

FIG. 15 shows the Path Check Inhibit 1 routine PC11.

STEP 1. This step causes the Path Check Inhibit 1 routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andthe action to be taken as follows:

If data D, is present for both Plane 0 and Plane 1 is no discrepancystep 6 is performed.

If discrepant data, DIS D, is present, step 3 is performed.

If data D is present for Plane 0, and Plane 1 is idle I, step 6 isperformed.

If data D is present for Plane 0, and path check pattern 0, PCO, ispresent for Plane 1, step 3 is performed.

If data D is present for Plane 0, and path check 1, PC1, is present forPlane 1 step 3 is performed.

If both planes are idle I, step 7 is performed.

If Plane 0 is idle, I, and data D, is present for Plane 1, step 7 isperformed.

If Plane 0 is idle I, and path check 0 PC0, is present for Plane 1, step7 is performed.

If Plane 0 is idle I, and path check 1 PC1, is present for Plane 1, step7 is performed.

STEP 3. This step causes the speech fault bit to be set.

STEP 4. This step causes the faulty timeslot number in the speech faultregister to be set to the current timeslot number.

STEP 5. This step causes the fault type in the speech fault register tobe set to pattern 0.

STEP 6. This step causes Plane 0 data to be sent to the peripheral.

STEP 7. This step causes Plane 1 data to be sent to the peripheral.

STEP 8. This step causes exit from the Path Check Inhibit 1 routine.

FIG. 16 shows the Path Check Inhibit 2 routine.

STEP 1. This step causes the Path Check Inhibit 2 routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andaction to be taken as follows:

If data D, is present for both Plane 0 and Plane 1, step 6 is performed.

If discrepant data, DIS D, is present, step 3 is performed.

If data D is present for Plane 0, and Plane 1 is idle I, step 6 isperformed.

If data D is present for Plane 0 and path check 0, PC0, is present forPlane 1, step 3 is performed.

If data D is present for Plane 0, and path check 1, PC1, is present forPlane 1, step 3 is performed.

If both planes are idle I, step 6 is performed.

If Plane 0 is idle I, and Plane 1 has data D present, step 6 isperformed.

If Plane 0 is idle, I and Plane 1 has path check 0, PC0, present, step 6is performed.

If Plane 0 is idle, I and Plane 1 has path check 1, PC1; present, step 6is performed.

STEP 3. This step causes the speech fault bit to be set.

STEP 4. This step causes the faulty timeslot number in the speech faultregister to be set to the current timeslot number.

STEP 5. This step causes the fault type in the speech fault register tobe set to pattern 0.

STEP 6. This step causes exit from the Path Check Inhibit 2 routine.

FIG. 17 shows a Checking routine CHK.

STEP 1. This step causes the Checking routine to be entered.

STEP 2 and STEP 3. These steps switch on a path state, and determines ifit is path checking on or off. If it is path checking on, step 5 isperformed. If it is path checking off, step 4 is performed.

STEP 4. This step causes a Valid routine to be performed, as describedwith reference to FIG. 24.

STEP 5. This step sets the path state to path checking off.

STEP 6. This step causes Plane 0 data to be sent to the peripheral.

STEP 7. This step causes exit from the Checking routine.

FIG. 18 shows a Persist routine. PST.

STEP 1. This step causes the Persist routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andthe action to be taken.

If data D, is present for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 4 is performed.

If data D is available for Plane 0 and Plane 1 is idle, I; step 3 isperformed.

If data D is available for Plane 0, and Plane 1 has path check 0, PC0;present, step 4 is performed.

If data D is available for Plane 0, and Plane 1 has path check 1, PC1;present, step 4 is performed.

If both planes are idle I,I; step 7 is performed.

If Plane 0 is idle I, and data D is present for Plane 1, step 7 isperformed.

If Plane 0 is idle I, and Plane 1 has path check 0, PC0; present, step 7is performed.

If Plane 0 is idle I, and Plane 1 has path check 1, PC1; present, step 7is performed.

STEP 3. This step causes Plane 0 data to be sent to the peripheral.

STEP 4. This step causes the path state to be in path checking on.

STEP 5. This step causes the speech fault bit to be set.

STEP 6. This step causes Plane 0 data to be sent to the peripheral.

STEP 7. This step causes Plane 1 data to be sent to the peripheral.

STEP 8. This step causes exit from the Persist routine.

FIGS. 19, 19a, 19b and 19c shows the Looking for Pattern 0 routine, LP0.

STEP 1. This step causes the Looking for Pattern 0 routine to beentered.

STEP 2. This step determines the data content of Plane 0 and Plane 1,and the action to be taken as follows:

If data D, is available for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 4 is performed.

If data D, is available for Plane 0, and Plane 1 is idle I, step 3 isperformed.

If data D is available for Plane 0, and Plane 1 has path check 0, PC0;present, step 6 is performed.

If data D is available for Plane 0, and Plane 1 has path check 1, PC1;present, step 4 is performed.

If both planes are idle I,I, step 21 is performed.

If Plane 0 is idle I, and data D is available for Plane 1, step 21 isperformed.

If Plane 0 is idle I, and Plane 1 has path check 0, PC0; present, step14 is performed.

If Plane 0 is idle I, and Plane 1 has path check 1, PC1; present, step21 is performed.

STEP 3. This step causes Plane 0 data to be sent to the peripheral.

STEP 4. This step causes the path state to be forced to path checkingon.

STEP 5. This step causes Plane 0 data to be sent to the peripheral.

STEP 6. This step determines the fault type in the speech fault registerand the action to be taken as follows:

If Checking for Discrepancy is present, step 7 is performed.

If Pattern 0 is present, step 7 is performed.

If Pattern 1, is present, step 10 is performed.

If Bias is present, step 10 is performed.

STEP 7. This step causes the faulty timeslot number in the speech faultregister to be set to the current timeslot number.

STEP 8. This step causes the fault type in the speech fault register tobe set to pattern 1.

STEP 9. This step causes the peripheral card controller to be put in astate: Looking for Pattern 1.

STEP 10. This step determines whether the current timeslot number equalsthe number stored in the speech fault register. If it does not, step 12is performed. If it does, step 11 is performed.

STEP 11. This step causes the peripheral card controller to be put in astate: Looking for Pattern 1.

STEP 12. This step causes the path state to be put to Path Checking On.

STEP 13. This step causes Plane 0 data to be sent to the peripheral.

STEP 14. This step determines the fault type in the speech faultregister and the action to be taken as follows:

If Checking for Discrepancy is present, step 13 is performed.

If Pattern 0 is present, step 15 is performed.

If Pattern 1 is present, step 18 is performed.

If Bias is present, step 18 is performed.

STEP 15. This step causes the faulty timeslot number in the speech faultregister to be set to the current timeslot number.

STEP 16. This step causes the fault type in the speech fault register tobe set to Pattern 1.

STEP 17. This step ensures that the peripheral card controller is in thestate: Looking for Pattern 1.

STEP 18. This step determines whether the current timeslot number isequal to the timeslot number stored in the speech fault register. If itdoes not, step 20 is performed. If it does, step 19 is performed.

STEP 19. This step ensures that the peripheral card controller is in thestate: Looking for Pattern 1.

STEP 20. This step causes Plane 1 data to be sent to the peripheral.

STEP 21. This step causes Plane 1 data to be sent to the peripheral.

STEP 22. This step causes exit from the Looking for Pattern 0 routine.

FIG. 20 shows the Looking for Pattern 1 routine, LP1.

STEP 1. This step causes the Looking for Pattern 1 to be entered.

STEP 2 and STEP 3. These steps cause the switch on of the path state. Ifthe path state is path checking off, PC OFF, step 4 is performed. If itis path checking is on, PC ON, step 5 is performed.

STEP 4. This step causes Path Check Checking for a Discrepancy routineto be performed, and is described with reference to FIG. 25.

STEP 5. This step causes Path Check Pattern 1 routine to be performedand is described with reference to FIG. 26.

STEP 6. This step causes exit from the Looking for Pattern 1 routine.

FIG. 21 shows the Path Check Continue routine, PCC.

STEP 1. This step causes the Path Check Continue routine to be entered.

STEPS 2 and 3. These steps cause switch on of the path state. If thepath state is Path Checking off, PC OFF, step 4 is performed. If it ispath cheching on, PC ON, step 5 is performed.

STEP 4. This step causes Path Check Checking for a Discrepancy, routineto be performed and is described with reference to FIG. 25.

STEP 5. This step causes Path Check Bias, routine to be performed and isdescribed with reference to FIG. 27.

STEP 6. This step causes exit from the Path Check Continue routine.

FIGS. 22 and 22a show the Plane Select routine PS.

STEP 1. This step causes the Plane Select routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1,and the action to be taken as follows:

If data D, is available for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 5 is performed.

If data D is available for Plane 0, and Plane 1 is idle I, step 3a isperformed.

If data D is available for Plane 0, and Plane 1 has Path Check 0, PC0present; step 5 is performed.

If data D is available for Plane 0, and Plane 1 has Path Check 1present, PC 1, step 5 is performed.

If both planes are idle I,I; step 3c is performed.

If Plane 0 is idle I, and data D is available for Plane 1, step 3c isperformed.

If Plane 0 is idle I, and Plane 1 has Path Check 0 PC0; present, step 3cis performed.

If Plane 0 is idle I, and Plane 1 has Path Check 1, PC1; present, step3c is performed.

STEP 3. This step causes Plane 0 data to be sent to the peripheral.

STEP 3a. This step determines if the path state is `Path Checking On`.If it is step 5 is performed, if not step 3b is performed.

STEP 3b. This step causes Plane 0 data to be sent to the peripheral.

STEP 3c. This step determines if the path state is `Path Checking On`.If it is step 5 is performed, if not step 4 is performed.

STEP 4. This step causes Plane 1 data to be sent to the peripheral.

STEP 5. This step determines whether the fault type in the faultregister is Continue. If not step 7 is performed. If it is, step 6 isperformed.

STEP 6. This step causes Plane 1 data to be sent to the peripheral.

STEP 7. This step causes Plane 0 data to be sent to the peripheral.

STEP 8. This step causes exit from the Plane Select routine.

FIG. 23 shows the Bias Transmit routine BST.

STEP 1. This step causes the Bias Transmit routine to be entered.

STEP 2. This step determines whether the loop back bit is set for eitherPlane 0 or Plane 1. If not, step 6 is performed. If it is, step 3 isperformed.

STEP 3. This step causes the loop back bits to be switched on. If theloop back bit for plane 0 LBP0 is switched on, step 4 is performed. Ifthe loop back bit for plane 1 LBP1 is switched on, step 5 is performed.

STEP 4. This step causes the transmission of switch data for Plane 0,and the transmission of peripheral data for Plane 1.

STEP 5. This step causes the transmission of peripheral data for Plane0, and the transmission of switch data for Plane 1.

STEP 6. This step causes the transmission of peripheral data for bothplanes.

STEP 7. This step causes exit from the Bias Transmit routine.

FIGS. 24 and 24a shows a Valid routine, VAL.

STEP 1. This step causes the Valid routine to be entered.

STEP 2. This step determines the state of Plane 0 and Plane 1 and theaction to be taken as follows:

If data D, is available for Plane 0 and 1, step 3 is performed.

If discrepant data, DIS D, is present step 5 is performed.

If data D is available for Plane 0, and Plane 1 is idle I, step 3 isperformed.

If data D is available for Plane 0, and Plane 1 has Path Check 0, PC0;present step 5 is performed.

If data D is available for Plane 0, and Plane 1 has Path Check 1, PC1;present step 5 is performed.

If both planes are idle, I,I; step 4 is performed.

If Plane 0 is idle I, and data D is available for Plane 1; step 4 isperformed.

If Plane 0 is idle I, and Plane 1 has Path Check 0, PC0; present step 4is performed.

If Plane 0 is idle, I, and Plane 1 has Path Check 1, PC1; present step 4is performed.

STEP 3. This step causes Plane 0 data to be sent to the peripheral.

STEP 4. This step causes Plane 1 data to be sent to the peripheral.

STEP 5. This step causes the speech fault bit to be set.

STEP 6. This step causes the path state to be set to Path Checking ON.

STEP 7. This step causes the faulty timeslot number in the speech faultregister to be set to the current timeslot number.

STEP 8. This step causes the fault type in the speech fault register tobe set to Pattern 0.

STEP 9. This step sets the peripheral card controller state toPersisting Discrepancy.

STEP 10. This step causes Plane 0 data to be sent to the peripheral.

STEP 11. This step causes exit from the Valid routine.

FIG. 25 shows a Path Check Checking for Discrepancy routine, CFD.

STEP 1. This step causes the Path Check Checking for Discrepancy routineto be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andthe action to be taken as follows:

If data D, is available for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 4 is performed.

If data D is available for Plane 0, and Plane 1 is idle I, step 3 isperformed.

If data D is available for Plane 0, and Plane 1 has in Path CheckPattern 0, present step 4 is performed.

If data D is available for Plane 0, and Plane 1 has Path Check Pattern 1present, step 4 is performed.

If both Planes are idle I,I, step 6 is performed.

If Plane 0 is idle I, and data D is available for Plane 1, step 6 isperformed.

If Plane 0 is idle I, and Plane 1 has Path Check Pattern 0 present, step6 is performed.

If Plane 0 is idle I, and Plane 1 has Path Check Pattern 1 present, step6 is performed.

STEP 3. This step causes Plane 0 data to be sent to the peripheral.

STEP 4. This step causes the path state to be set to Path Checking On.

STEP 5. This step causes Plane 0 data to be sent to the peripheral.

STEP 6. This step causes Plane 1 data to be sent to the peripheral.

STEP 7. This step causes exit from the Path Check Checking forDiscrepancy routine.

FIGS. 26 and 26a show a Path Check Pattern 1 routine PCP1.

STEP 1. The step causes the Path Check Pattern 1 routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andthe action to be taken as follows:

If data D, is available for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 3 is performed.

If data D is available for Plane 0, and Plane 1 is idle I, step 3 isperformed.

If data D is available for Plane 0, and Plane 1 has Path Check 0 PC0present; step 3 is performed.

If data D is available for Plane 0, and Plane 1 has Path Check 1 PC1present; step 6 is performed.

If both Plane are idle I,I, step 3 is performed.

If Plane 0 is idle I, and data D is available for Plane 1, step 14 isperformed.

If Plane 0 is idle I, and Plane 1 has Path Check 0 PC0 present; step 14is performed.

If Plane 0 is idle I, and Plane 1 has Path Check 1 PC1 present; step 10is performed.

STEP 3. This step determines whether the current timeslot number isequal to the timeslot number stored in the speech fault register. If itdoes not, step 5 is performed. If it does step 4 is performed.

STEP 4. This step sets the peripheral card controller to the state:Looking for Pattern 0.

STEP 5. This step causes Plane 0 data to be sent to the peripheral.

STEP 6. The step determines whether the current timeslot number is equalto the number stored in the speech fault register. If it does not, step9 is performed. If it does step 7 is performed.

STEP 7. This step causes the fault type in the speech fault register tobe set to Continue.

STEP 8. This step sets the peripheral card controller to the state: PathCheck Continue.

STEP 9. This step causes Plane 0 data to be sent to the peripheral.

STEP 10. This step determines whether the current timeslot number equalsthe number stored in the speech fault register. If it does, step 13 isperformed. If it does, step 11 is performed.

STEP 11. This step causes the faulty type in the fault register to beset to Continue.

STEP 12. This step sets the peripheral card controller to the state:Path Check Continue.

STEP 13. This step causes Plane 1 data to be sent to the peripheral.

STEP 14. This step determines whether the current timeslot number equalsthe number stored in the speech fault register. If it does not, step 16is performed. If it does, step 15 is performed.

STEP 15. This step sets the peripheral card controller to the state:Looking for Pattern 0.

STEP 16. This step causes Plane 1 data to be sent to the peripheral.

STEP 17. This step causes exit from the Path Check Pattern 1 routine.

FIG. 27 shows the Path Check Bias routine PCB.

STEP 1. This step causes the Path Check Bias routine to be entered.

STEP 2. This step determines the data content of Plane 0 and Plane 1 andthe action to be taken as follows:

If data D, is available for Plane 0 and Plane 1, step 3 is performed.

If discrepant data, DIS D, is present, step 3 is performed.

If data is available for Plane 0, and Plane 1 is idle, step 4 isperformed.

If data is available for Plane 0, and Plane 1 has Path Check 0, PC0present; step 4 is performed.

If data is available for Plane 0, and Plane 1 has Path Check 1, PC1present; step 4 is performed.

If both planes are idle I,I, step 3 is performed.

If Plane 0 is idle, I and data is available for Plane 1, step 3 isperformed.

If Plane 0 is idle I, and Plane 1 has Path Check 0, PC0 present; step 3is performed.

If Plane 0 is idle I, and Plane 1 has Path Check 1, PC1 present; step 3is performed.

STEP 3. This step causes Plane 1 data to be sent to the peripheral.

STEP 4. This step causes Plane 0 data to be sent to the peripheral.

STEP 5. This step causes exit from the Path Check Bias routine.

Waveform Distribution

A waveform generator provides three basic clocks to a waveformdistributor. The distributor generates all the other waveforms requiredwithin the limits of those supplied by the generator.

Timing information is distributed across the control/switch orswitch/peripheral boundaries by encoding it into a 2.048Mb/s datastream. Within the functional areas the appropriate timing informationcan be extracted from the data stream.

Timing from the generator is passed by way of the distributor to aduplicated system comprising the two control/switch planes. Both planesfinally drive into a peripheral unit. The common point in the peripheralunit will be the peripheral card controller. The peripheral cardcontroller validates each clock stream received from both planes. If theperipheral card controller decides that both planes have valid clockstreams, then it will select one plane arbitrarily. This will mean thatdifferent peripherals may be being driven by clocks from differentplanes. Therefore the clocks provided for each plane by the distributormust be derived from the same generator to ensure phase coherence.

It will be appreciated by those skilled in the art, that the hardwarenecessary to perform the invention, such as fault registers, countersetc. are types of standard equipment, the function of which is wellknown in the art.

We claim:
 1. In a security telecommunications system having a pluralityof peripherals respectively connected to corresponding peripheral cardcontrollers interconnected by switching arrangements, said switchingarrangements being respectively duplicated to form two security planesand transmitting data during time slots, a method wherein each of theperipheral card controllers performs the steps of: detectingdiscrepancies between data transmitted from the switching arrangementsunder no fault conditions with respect to each of the time slots;monitoring a path provided between the peripheral card controllers inresponse to said detection of the discrepancies for appearances of afirst test pattern during said time slots; identifying the time slotsduring which the first test patterns appear on the path; monitoring saidpath for appearances of a second test pattern in said identified timeslots; and detecting the absence of the second test pattern on themonitored path in the identified time slots to signify that one of thesecurity planes is faulty.
 2. A security arrangement as claimed in claim1 wherein the path monitoring steps are performed by the peripheral cardcontrollers transmitting the test patterns to the switching arrangementsfor all timeslots for which a discrepancy is detected.
 3. A securityarrangement as claimed in claim 2 wherein each of the peripheral cardcontrollers is arranged to monitor data received from the switchingarrangement through which the test patterns are to be returned.
 4. Asecurity arrangement as claimed in claim 2, wherein the test patternsare relatively inverse, and are alternated.
 5. A security arrangement asclaimed in claim 4 wherein the path is a duplex path.
 6. A securityarrangement as claimed in claim 1 wherein the path monitoring steps isan algorithm which utilizes the condition of the peripheral cardcontrollers as a whole and the condition of each of the identifiedtimeslots.